[Simh] Another PDP11 "approximation" (was: DMA to IO page)

[Bob Supnik]

The discussion about the peculiarities of accessing the MK11 CSRs shows
another limitation of SimH for Unibus systems: the Unibus memory space
part of the address space of an 11/70 simply isn't there. The ReadB/W
and WriteB/W routines in the CPU are very simple: if it's memory, it's
in the M array; if it's in the IO page, it's accessed via a device
dispatch routine. Anything in between is NXM. There's no provision for
configuring or accessing Unibus memory or, worse yet, "reflecting" a
Unibus memory space operation back into real memory to get at CSRs. And
max memory is 4088KB, not 3840KB.

Again, this reflects the Qbus (and specifically, the KDJ11A) origins of
the PDP11 simulator. In a 22b Qbus system, everything except the last
8KB is memory space. In fact, a Qbus system can have (electrically) a
full 4096KB of memory, and DMA devices can access all of it, because
unless BBS7 is asserted, everything is memory, and the address space is
flat.

While the 11/70 required a convoluted "reflection" of CSR accesses back
into memory space, later Unibus maps (like the 11/24 and 11/44) solved
this problem more simply, by sending IO space addresses out on the 22b
private memory bus as well as the Unibus. Except for the memory CSRs,
these addresses are ignored. If the memory bus responds to an IO page
reference, the Unibus operation is stopped; there is no Unibus NXM. No
reflection logic is required or implemented. According to the 11/70
documentation, a later "modification" of the CPU allowed this same
approach to be used on the 11/70.

So what does this mean, in practice?

- Except for an unmodified 11/70, accessing memory CSRs just requires
the current IO page dispatch methods. The simulator has no concept of
"memory bus" vs "Unibus" (or internal registers versus Unibus); anything
in the IO page is accessed the same way, which is just fine. Of course,
none of the memory CSRs are implemented anyway.

- Unless there's a use case for Unibus memory on a 22b Unibus system, I
don't see any point in adding it.

- If you want to improve the fidelity of the simulation a bit, the "4M"
memory size setting could be adjusted to 3840 vs 4088, for U vs Q, in
the cpu_set_size routine.

/Bob Supnik

[Johnny Billquist]

Post by Bob Supnik
The discussion about the peculiarities of accessing the MK11 CSRs shows
another limitation of SimH for Unibus systems: the Unibus memory space
part of the address space of an 11/70 simply isn't there. The ReadB/W
and WriteB/W routines in the CPU are very simple: if it's memory, it's
in the M array; if it's in the IO page, it's accessed via a device
dispatch routine. Anything in between is NXM. There's no provision for
configuring or accessing Unibus memory or, worse yet, "reflecting" a
Unibus memory space operation back into real memory to get at CSRs. And
max memory is 4088KB, not 3840KB.
Again, this reflects the Qbus (and specifically, the KDJ11A) origins of
the PDP11 simulator. In a 22b Qbus system, everything except the last
8KB is memory space. In fact, a Qbus system can have (electrically) a
full 4096KB of memory, and DMA devices can access all of it, because
unless BBS7 is asserted, everything is memory, and the address space is
flat.
While the 11/70 required a convoluted "reflection" of CSR accesses back
into memory space, later Unibus maps (like the 11/24 and 11/44) solved
this problem more simply, by sending IO space addresses out on the 22b
private memory bus as well as the Unibus. Except for the memory CSRs,
these addresses are ignored. If the memory bus responds to an IO page
reference, the Unibus operation is stopped; there is no Unibus NXM. No
reflection logic is required or implemented. According to the 11/70
documentation, a later "modification" of the CPU allowed this same
approach to be used on the 11/70.
So what does this mean, in practice?
- Except for an unmodified 11/70, accessing memory CSRs just requires
the current IO page dispatch methods. The simulator has no concept of
"memory bus" vs "Unibus" (or internal registers versus Unibus); anything
in the IO page is accessed the same way, which is just fine. Of course,
none of the memory CSRs are implemented anyway.
- Unless there's a use case for Unibus memory on a 22b Unibus system, I
don't see any point in adding it.
- If you want to improve the fidelity of the simulation a bit, the "4M"
memory size setting could be adjusted to 3840 vs 4088, for U vs Q, in
the cpu_set_size routine.

The 3840 limit is not universal for Unibus machines. As you noted
yourself, other Unibus -11s are different. I no longer remember exactly
how the 11/24 and 11/44 behaves, but I know that the 11/84 and 11/94
allows up to 4088 KB of main memory. The Unibus map on those machines
are only exposed to the Unibus side, for DMA. Memory sits on the PMI
side, before the Unibus map, and so the CPU gets to all memory directly.

So, this would probably have to be very 11/70 specific.

As for the CSRs on the MK11, the 11/70 was modified to get direct access
to the MK11 CSRs as a part of the changes for the 11/74. I am not aware
of any "standard" 11/70 that can do it.
However, it's of limited value perhaps, since without them, it just
appears as if the 11/70 would have MJ11 memory boxes instead, which do
not have any CSRs. So the emulation is not strictly necessary in order
to appear as a correct 11/70 machine.

But thanks for the further explanations of the innards of simh.
And I'm not trying to point any fingers because of how simh was
designed. There are limitations, but as you note, it was correct for the
targets you started with.

Johnny